隨手記錄

Principles of Scan Testing

- Advanced Topic -

掃描測試的原理

- 進階主題 -

⬛Objectives:

This section explains:

• The purpose of scan testing

• The benefits of scan testing

• Device types that benefit from scan testing

• Scan test circuitry

• Equipment required for scan testing

目標

本節解釋

• 掃描測試的目的

• 掃描測試的好處

• 受益於掃描測試的元件類型

• 掃描測試電路

• 掃描測試所需的設備

⬛What is Scan Testing?

什麼是掃描測試？

Scan testing is a way of decreasing the test development time and test time for certain types of devices. It depends on designing special test circuits into the devices (called Scan design). Scan Design is a structured design methodology that greatly reduces the complexity of functional test generation. The philosophy is one of "divide and conquer" and can best be described with reference to the general model for a clocked (synchronous) logic circuit shown in Figure 16-1.

掃描測試是一種減少某些類型元件的測試開發時間和測試時間的方法。它取決於在元件中設計特殊的測試電路（稱為掃描設計）。掃描設計是一種結構化的設計方法，大大降低了功能測試生成的複雜性。它的理念是 "分而治之"，最好參照圖16-1所示的時脈（同步）邏輯電路的一般模型來描述。

In this model, the major elements of the circuit are identified as a combinational logic section together with a bank of memory elements M1, M2, ..., Mn under control of a system clock. Inputs to the combinational logic consist of the device inputs (Primary Inputs) and then fed back secondary-state variables from the memory elements. The device outputs (Primary Outputs) are therefore a function of the present state of the device inputs together with the current states of the memory elements.

在這個模型中，電路的主要元素被識別為一個組合邏輯部分和一個由系統時鐘控制的記憶元件庫M1、M2、...、Mn。組合邏輯的輸入包括設備輸入（初級輸入），然後從記憶元件回饋二級狀態變數。因此，元件輸出（初級輸出）是元件輸入的當前狀態和記憶元件的當前狀態的函數。

The future state of the memory elements also depends on both the primary inputs and the current recorded state of the memory elements themselves. It is this dependency of the future state on the present state that causes all the problems in test generation. The device inputs are the only inputs the test has direct control o and likewise, the device outputs are the only outputs the test can directly observe. The problem is which section can be tested first since neither section is directly controllable or observable and the sections are mutually dependent on each other for correct operation.

記憶元件的未來狀態也取決於主要輸入和記憶元素本身的目前記錄狀態。正是這種未來狀態對當前狀態的依賴性，導致了測試生成中的所有問題。元件輸入是測試唯一可以直接控制的輸入，同樣，元件輸出也是測試唯一可以直接觀察的輸出。問題是哪個部分可以先被測試，因為這兩個部分都不能直接控制或觀察，而且這兩個部分的正確操作是相互依賴的。

The scan design methodology provides a solution to this problem by reducing the complexity of the circuit. Scan designs are based on the principle of providing the following test facilities:

1. All memory elements can be tested in isolation from the rest of the circuit.

2. The future state of the secondary-state variables can be set to any value independent of their present values.

3. The outputs of the combinational logic that drive into the memory elements can be observed directly.

掃描設計方法通過降低電路的複雜性為這個問題提供了一個解決方案。掃描設計是基於提供以下測試設施的原則。

1. 所有的記憶體元件都可以與電路的其他部分隔離開來進行測試。

2. 次級狀態變數的未來狀態可以被設置為獨立於其當前值的任何數值。

3. 可以直接觀察驅動進入記憶體元件的組合邏輯的輸出。

Scan design is implemented by establishing a scan path through the memory element as shown in Figure 2. Effectively, each memory element is now preceded by a 2-way switch (multiplexer) under the control of a common Scan Select signal. When Scan Select is off, the multiplexers connect the outputs from the combinational logic to the input sides of the memory elements, i.e. the circuit functions in its normal mode When Scan Select is on, the memory elements are reconfigured into an isolated serial-in, serial-out shift register.

如圖2所示，掃描設計是通過建立一個通過記憶元件的掃描路徑來實現的。實際上，現在每個記憶元件前面都有一個由共同的掃描選擇信號控制的2路開關（多工器）。當 "掃描選擇 "關閉時，多工器將組合邏輯的輸出連接到記憶元件的輸入端，即電路在其正常模式下運行。"掃描選擇 "打開時，記憶元件被重新配置為一個隔離的串列輸入、串行輸出移位暫存器。

The serial data input is called Scan Data In and the serial data output is called Scan Data Out. In the scan mode, the memory elements can be preset to any particular set of values simply by placing the values in sequence on the Scan Data In input and clocking the shift register with the System Clock. The testing strategy now becomes:

串列資料登錄被稱為掃描資料登錄，串列資料輸出被稱為掃描資料輸出。在掃描模式下，記憶體元件可以被預設為任何特定的值，只需將這些值依次放在掃描資料登錄端上，然後用系統時脈給移位暫存器計時。現在的測試策略變成了。

1. Select the scan-path mode, i.e. memory elements reconfigured into a shift register. Test the status and operation of each memory element using the Scan Data In, Scan Data Out, and System Clock facilities. Suitable tests for a scan-path register are as follows:

1. 選擇掃描路徑模式，即記憶體元素重新配置成移位暫存器。使用掃描資料登錄、掃描資料輸出和系統時鐘設施測試每個存儲元素的狀態和操作。適合於掃描路徑寄存器的測試如下。

a. FLUSH TEST- In this test all memory elements are initialized to logic 0 and a single logic 1 is clocked through from the Scan Data In input to the Scan Data Out output using the scan path (system) clock. The procedure can be repeated with a single logic 0 flushed through a background of logic 1s. This sequence checks the ability of each memory element to assume both logic states.

b. SHIFT TEST - In this test, the data sequence 00110011.. is shifted through the register. This sequence exercises each memory element through all combinations of the present state and future state.

a. 沖洗測試-在這個測試中，所有的記憶體元素都被初始化為邏輯0，並且使用掃描路徑（系統）的時震從掃描資料登錄端到掃描資料輸出端的單一邏輯1。這個過程可以重複進行，用一個邏輯0沖過一個邏輯1的背景。這個序列檢查了每個存儲元素承擔兩種邏輯狀態的能力。

b. 移位元測試 - 在這個測試中，資料序列00110011...在寄存器中被移位。這個序列通過當前狀態和未來狀態的所有組合來鍛煉每個記憶元件。

2. Determine a set of tests for the combinational logic, assuming

a. total control of all inputs (primary and from the memory elements);

b. direct observation of all outputs (primary and to the memory elements).

2. 確定一套組合邏輯的測試，假設

a. 完全控制所有的輸入（主要的和來自記憶元件的）。

b. 直接觀察所有的輸出（主要的和對記憶元件的）。

3. Apply each test in the following way:

a. Select scan-path mode. Load the memory elements with test input values and establish additional test input values on the primary inputs.

b. Select normal mode. The steady-state output response of the combinational logic can now be clocked into the memory elements.

c. Return to scan-path mode and clock out the contents of the memory elements. Compare these values, plus the values directly observable on the primary outputs, with the expected response.

3. 以下列方式應用每個測試。

a. 選擇掃描路徑模式。用測試輸入值載入記憶元件，並在主輸入上建立額外的測試輸入值。

b. 選擇正常模式。組合邏輯的穩態輸出回應現在可以通過時鐘進入記憶元件。

c. 返回到掃描路徑模式，將記憶元件的內容時脈化。將這些值，加上在主輸出上可直接觀察到的值，與預期的回應進行比較。

The philosophy of the scan design can now be seen more clearly. Rather than test the circuit as a single entity. the addition of the scan path allows each major segment to be tested separately and in a procedural manner. Standard tests can be defined for the memory elements (Step 1. above). The only test-generation problem is to generate tests for the combinational segment. This problem has been well researched and a variety of logic or fault simulators can be used.

現在可以更清楚地看到掃描設計的理念。而不是把電路作為一個單一的實體來測試。掃描路徑的增加使得每個主要的部分都能以程式的方式被單獨測試。可以為記憶體元件定義標準測試（步驟1.以上）。唯一的測試生成問題是為組合段生成測試。這個問題已經得到了很好的研究，各種邏輯或故障模擬器都可以使用。

⬛LSSD Technique.

LSSD技術

A number of circuit design techniques have been developed to implement the scanning methodology with Level Sensitive Scan Design (LSSD), developed by IBM Corp. receiving the most attention. LSSD is specifically aimed at reducing the dependency of system operation on AC parameters such as clock edge rise or fall times. which are difficult to simulate in the design environment and difficult to monitor in a manufacturing environment.

一些電路設計技術已經被開發出來以實現掃描方法，其中由IBM公司開發的位準敏感掃描設計（LSSD）受到了最多的關注。LSSD的具體目標是減少系統操作對交流參數的依賴性，如時脈邊緣上升或下降時間，這在設計環境中很難模擬，在製造環境中也很難監測。

The technique provides direct control of two clocks. One clock controls the acceptance of data into the memory elements while the second clock controls their outputs. With direct clock control, the timing of the circuit can be controlled to avoid potential race conditions resulting from the primary or secondary inputs propagating through the combinational circuits.

該技術提供對兩個時脈的直接控制。一個時脈控制資料是否可進入記憶體元件，而第二個時脈則用來控制它們的輸出。通過直接的時脈控制，可以控制電路的時間，以避免主要或次要輸入通過組合電路傳播而產生的潛在競速條件。

⬛Scan Test Equipment

掃描測試設備

The total number of memory elements in a VLSI circuit can result in a very long scan path shift register (scan chain). Memory elements are often divided into multiple scan chains to simplify and speed up testing. Since scan test patterns are serial representations of the circuit states, it is not uncommon for these patterns to be millions of vectors long. Standard functional test pattern memory is designed to supply high-speed parallel (pin wide) data and is not cost-effective for scan testing.

一個VLSI電路中的儲存元件的總數會導致一個很長的掃描路徑移位暫存器（掃描鏈）。記憶體元件通常被分成多個掃描鏈，以簡化和加快測試。由於掃描測試模式是電路狀態的串列表示，這些模式長達數百萬個向量是很常見的。標準的功能測試模式記憶體是為提供高速並行（引腳寬）資料而設計的，對於掃描測試來說並不經濟。

Test equipment designed for scan testing has two functional test pattern memories. One is for parallel (pin wide) data and another is for serial (scan) data. Each tester channel (pin) can be programmed to use the parallel or serial test pattern. The serial memory is generally two bits wide (serial data in and out) and can be configured into multiple depth/width ratios under program control.

為掃描測試設計的測試設備有兩個功能測試模式記憶體。一個是並行（引腳寬）資料，另一個是串列（掃描）資料。每個測試通道（針腳）可以被程式設計為使用並行或串列測試模式。串列記憶體一般是兩位元寬（串列資料的輸入和輸出），在程式控制下可以配置成多種深度/寬度比例。