隨手記錄

半導體測試 常用語彙

以下記錄半導體測試常用的名詞、語彙，並依照英文字母順序排列。以便有需要時，可以上來查詢。

 

 

AC Testing

■ AC Testing

● AC testing guarantees that the device meets all of the timing specifications. AC testing is performed by setting up the appropriate timing values (edge placements) and signal formats as defined in the device AC specifications and then executing a functional test sequence.

● AC測試是要確保元件符合時序規格。AC測試的作法是依照元件的AC規格設定適合的時序値(邊緣放置)與訊號格式，並且執行功能測試順序。

 

 

 

Assembly Verification

■ Assembly Verification

● Assembly verification is primarily to verify that the devices survived the assembly process and that they were assembled correctly. The tests performed during assembly verification are similar to that of package testing and maybe a subset of package testing.

● 組裝驗證主要爲驗證元件組裝過程未受損毀，並且組裝正確。組裝驗證的所作的測試是與封裝測試相似。

 

 

Bi-directional Pin

■ Bi-directional Pin

● A device pin that functions as an input, an output, and is also capable of turning off (going to a high impedance state).

● 雙向腳位是一種元件腳位，其可作爲輸入腳及輸出腳，也能關閉成高阻抗的狀態。

 

 

 

Binning

■ Binning

● A means of categorizing or sorting the tested devices into their appropriate groupings, either hardware bins or software bins.

● 一種將測試過的元件分成適當的組別的分類方式。有硬體分類與軟體分類。

 

 

Clamps

■ Clamps

● Hardware limits the amount of voltage or current that is supplied by the test system during a test. Clamps are used to protect the test operator, the test hardware, and the DUT.

● 在測試期間限制由測試系統的提供電壓或電流的硬體。

 

 

 

Comparators

■ Comparators

● The circuitry located on the pin electronics card senses the logic 0 and logic 1 levels from the DUT. The comparators are used during functional testing.

● 在腳位電子卡的比較器電路,能夠偵測出從 DUT 來的訊號 是邏輯0還是邏輯1。此比較器電路是在作功能測試時會使用到。

 

 

DC Testing

■ DC Testing

● When a voltage or current is measured during the test and the pass/fail results are based upon the measured value. The PMU is designed to perform DC tests.

● 測試為量測電流或電壓並根據量測值得到 pass/fail 結果。 DC 測試時是使用精密量測單元(PMU)。

 

 

 

Device Characterization

■ Device Characterization

● Device Characterization is the process of determining the operating extremes of devices.

● 是決定元件操作極限的程序。

 

 

Device Specification

■ Device Specification

● The device specification defines the exact performance conditions of the device. The specification includes voltages, currents, timings, and a description of the device's functions.

● 元件規格定義元件正確操作的條件。規格包括電壓、 電流、時序與元件功能的描述。

 

 

 

DPS

■ DPS

● Device Power Supplies are used to supply voltage and current directly to the DUT. The power pin (VDD or DCC) of the DUT will usually be connected to a DPS.

● 元件電源供應器(DPS)是用來提供待測元件電壓與電流。待測元件 的電源腳(Von 或 Vec)通常是與 DPS 相連接。

 

 

Drivers

■ Drivers

● The circuitry on the pin electronics card supplies the logic 0 and logic 1 levels to the DUT. A pin is said to be driven if the test system driver applies a voltage to it.

● 腳位電子卡上提供給待測元件邏輯0位準或邏輯1位準的電路。 當測試系統的驅動器(driver)施加電壓於待測元件,稱作腳位被驅動。

 

 

 

DUT

■ DUT

● The semiconductor device being tested is often referred to as the DUT (Device Under Test). It is also sometimes referred to as a UUT (Unit Under Test).

● 進行測試的半導體元件通常稱作 DUT(Device Under Test),有時也 稱作 UUT(Unit Under Test)。

 

 

 

Dynamic

■ Dynamic

● A term used to indicate that the DUT is actively changing states, dynamic tests are associated with executing functional test vectors.

● 是指 DUT 在改變狀態,動態測試時會配合功能測試向量執行。

 

 

 

 

Dynamic Loads

■ Dynamic Loads

● The circuitry is located on the pin electronics card acts as a load and can be programmed to supply positive and negative currents. The dynamic loads can be used to supply IOL and IOH currents for loading DUT outputs. Dynamic loads are also referred to as programmable current loads.

● 在腳位電子電路卡(pin electronics card)上有作爲負載的電路，此負載可由程式規劃成提供正電流或負電流。此動態負載電路可以用 來提供IOL與 IOH給 DUT 的輸出腳。動態負載也可稱爲可程式電流負載。

 

 

Failure Analysis

■ Failure Analysis

● Failure Analysis is the process of determining why a device has failed.

● 錯誤分析是決定爲何元件會錯誤過程。

 

 

 

 

FDATA

■ FDATA

● Formatted vector data (logic 1s and Os) combined with timing and signal format information.

● 結合時序與訊號格式資訊的格式化的向量資料(邏輯0和邏輯 1)。

 

 

Force Line

■ Force Line

● The force line is the current-carrying line of a four-wire system such as a power supply. The four wires of a four-wire system are the High Force, High Sense, Low Force, and Low Sense. In test systems, the Device Power Supply and the Precision Measurement Unit are four-wire systems.

● 在測試系統中, 元件電源供應器(Device Power Supply)與精密量單元(Precision Measurement Unit)為四線系統,四線系統的四線是 High Force、High Sense、Low Force與Low Sense。Force line 是如電源供應器的四線系統的電流運送線。

 

 

 

Forcing

■ Forcing

● The term force, as in forcing voltage or forcing current, is often used to describe certain activities during testing. Force is used to describing the act of applying a certain value of voltage or current by the test system. Apply can be substituted for the word force.

● 在測試時有施加電壓或施加電流的動作。Force 是用來描述測試 機施加電壓或施加電流的動作。

 

 

Functional Testing

■ Functional Testing

● When the device is actively performing logical functions. Input data is supplied to the DUT and output data is read from the DUT. The functional comparator circuitry located on the pin electronics cards is used to determine the pass/fail results of the test.

● 當元件在執行邏輯功能動作時。輸入資料爲被送至 派DUT 且輸出資料會被讀取，再使用腳位電子卡上的比較器以決定測試結 果是 pass 還是 fail。

 

 

 

Gross Testing

■ Gross Testing

● Performing a test with relaxed conditions (levels and timings) usually made to verify if the device is "functionally alive" without regard to the device specification parameter values.

● 以寬鬆的條件(位準或時序)執行的測試，測試時不一定使 用元件規格參數值，通常用在驗證元件功能是否正確。

 

 

Ground

■ Ground.

● To connect a signal pin or other electrical node to the test system reference node or to VSS.

● 連接訊號腳或其他電路節點到測試系統的參考節點或 Vss。

 

 

 

Hot Switching

■ Hot Switching

● Occurs when a relay is opened while current is flowing through it, or when the current immediately begins to flow after a relay is closed (i.e. when the two terminals of a relay are at different voltages when the relay is closed). Opening or closing a relay while current is flowing through it may result in damage to the relay. Through careful test programming, this can be avoided.

● 發生在當有電流在流動時繼電器被打開，或是在繼電器一 關上電流立刻開始流動(也就是當繼電器關閉時，繼電器兩端的電位不同)。在有電流流過繼電器時作關閉或打開的動作會損害繼電器。要小心的寫測試程式以避免此狀況發生。

 

 

ICC

■ ICC

● The current is consumed by the circuitry of a TTL device.

● TTL 元件的電流消耗

 

 

 

IDD

■ IDD

● The current is consumed by the circuitry of a MOS device.

● MOS 元件的電流消耗

 

 

IDDQ

■ IDDQ

● The IDDQ test measures the quiescent current under varying logic conditions and provides improved test coverage as compared to the standard Static IDD test.

● 測試量測在不同邏輯條件下的靜態電流

 

 

 

IIL

■ IIL

● Input Leakage Low is the maximum amount of current that is allowed to flow out of an input pin when a low voltage value is forced onto the pin.

● 當施加低電壓於輸入腳時，所允許流出輸入腳的最大電流量。

 

 

IIH

■ IIH

● Input Leakage High is the maximum amount of current that is allowed to flow into an input pin when a high voltage value is forced onto the pin.

● 當施加高電壓於輸入腳時，所允許流入輸入腳的最大電流量

 

 

 

Incoming Inspection

■ Incoming Inspection

● Incoming Inspection is performed by the customer to ensure the quality of the devices purchased before using them in an application.

● 進料測試是由客戶在將元件拿來使用前的品質確認動作。

 

 

 

Input Pin

■ Input Pin

● A device pin acts as a buffer between external signals and the internal logic of a device. The input senses the voltage which is applied to it and transmits a logic 0 or logic 1 level to the internal logic of the device.

● 元件的輸入腳作爲外部電路與內部電路的內部邏輯電路的緩衝器。輸入腳會偵測到被施加的電壓再傳遞邏輯0或邏輯1準位到元件內部的邏輯電路。

 

 

 

IO Conflicts

■ IO Conflicts

● A condition that exists when the test system and the DUT are simultaneously driving voltage into the same tester channel, is also called Bus Contention.

● 當測試系統與 DUT 同時對同一個測試通道送電壓的情況, 也稱作 Bus Contention。

 

 

IOH

■ IOH

● Current Out High is the amount of current that output must source when driving a logic 1. The output must be capable of supplying the specified IOH current while maintaining the correct VOH voltage.

● 當將輸出驅動到邏輯 1 所流出的電流量。當輸出維持在正確的VOH這位準時，輸出能夠在提供合規格的 IOH 電流量。

 

 

 

IOL

■ IOL

● Current Out Low is the amount of current that output must sink when driving a logic 0. The output must be capable of accepting the specified IOL current while maintaining the correct VOL voltage.

● 當將輸出驅動到邏輯 0 所承受的電流量。當輸出維持在正確的 Vol 位準時，輸出能夠在提供合規格的 IOL 電流量。

 

 

IO Switching

■ IO Switching

● The DUT alternates between receiving data from the test system (reading data) and supplying data to the test system (writing data). The same pin or set of pins functions as both inputs and outputs.

● DUT在從測試系統接收資料(讀資料)與提供資料給測試系統(讀資料)之間轉換。這組腳具有輸入腳與輸出腳的功能。

 

 

 

IOZH

■ IOZH

● Output High Impedance Leakage Current High is the maximum amount of current that is allowed to flow when a high voltage is applied to a bi-directional or three-state pin, and the pin is in the off or High-Z state.

● 當輸出爲關閉(off)或高阻抗狀態時，高位準電壓施加於雙向腳或三態腳時可以允許的最大漏電流值。

 

 

IOZL

■ IOZL

● Output High Impedance Leakage Current Low is the maximum amount of current that is allowed to flow when a low voltage is applied to a bi-directional or three-state pin, and the pin is in the off or High-Z state.

● 當輸出爲關閉(off)或高阻抗狀態時,低位準電壓施加於雙向腳或三態腳時可以允許的最大漏電流值。

 

 

 

Kelvin Connection

■ Kelvin Connection

● The Kelvin connection or Kelvin connect point is the point where the force and sense lines of a four-wire system are connected. Four-wire systems provide a very accurate method of supplying voltage or current to a remote location. In test systems, the Device Power Supply and the Precision Measurement Unit are four-wire systems.

● Kelvin 連接或 Kelvin 連接點爲四線系統的 force 線與 sense 線連在一起。DPS 與 PMU 爲四線系統。

 

 

Latch-up

■ Latch-up

● A high current condition that exists within a CMOS device is caused by applying an improper voltage level to a signal pin or by an improper voltage applied to VDD or ground. This condition can weaken the device or cause a catastrophic failure.

● 藉由施加不適當的電壓位準到訊號腳或不適當的電壓到 Vdd或接地端導致在 CMOS 元件中有高電流情況發生。當 Latch-up 發生會使元件損壞。

 

 

 

Margins

■ Margins

● Margins refer to the amount by which a parameter can be varied before a failure occurs.

● 指在錯誤不會發生的前提下參數可以變動的量。

 

 

Military Testing

■ Military Testing

● Military Testing involves performing more rigorous testing over temperature and documenting the results.

● 軍規測試是執行更嚴格的測試。

 

 

 

Negative Current

■ Negative Current

● Current flowing from the DUT into the test system.

● 電流從 DUT 流向測試系統爲負電流。
 

 

Noise Spike

■ Noise Spike

● When a signal level abruptly changes its voltage (and/or logic) level for a very short time. Sometimes called a Glitch.

● 當訊號在很短的時間內突然改變其電壓值。也稱作 Glitch。

 

 

 

Output Mask

■ Output Mask

● A method of enabling or disabling an output comparison for a tester channel during a functional test.

● 在作功能測試時，將測試通道的輸出比較器作致能或禁能。

 

 

Output Pin

■ Output Pin

● A device pin acts as a buffer between the internal logic of a device and the external environment. An output pin is capable of providing the correct voltages to produce a logic 0 or logic 1 level and also supplies the IOL/IOH current.

● 元件輸出腳作爲外部電路與內部電路的內部邏輯電路的緩衝器。輸出腳能提供正確的邏輯0或邏輯1電壓值並可提供IOH 與 IOL。

 

 

 

Output Sampling

■ Output Sampling

● The point in time at which the output signal of a DUT will be evaluated. The comparator circuitry will compare the output voltage to a pre-defined logic 1 or logic 0 levels. The test system will then make a pass/fail decision. Output sampling is also called the strobe.

● 要取得 DUT 的輸出訊號數值的時間點。比較電路會將 輸出電壓值與預先定義的邏輯 0 或邏輯 1 位準作比較。測試系統會作 pass/fail 的決定。也稱爲 strobe. 

 

 

Package Test

■ Package Test

● Wafers are cut into the individual die and each die is then assembled into a package. The packaged device is then tested to ensure that the assembly process was correctly performed and to verify that the device still meets its design specifications. The package test is also called the final test.

● 晶圓被切成一個一個的晶粒,每一個晶粒會被封裝。封裝 好的元件要再進行測試以確保在組裝過程是正確運轉的,並且驗元件依然 符合元件的設計規格。也稱爲 Final test。

 

 

 

Pattern Memory

■ Pattern Memory

● A high-speed memory that stores test vector information. Vector memory may also be called vector memory.

● 能夠儲存測試向量(test vector)訊息的高速記憶體。也可稱爲 vector memory。

 

 

Pin Electronics

■ Pin Electronics

● The circuitry is located in the test head that is used to supply input signals to the DUT and to receive output signals from the DUT. The pin electronics are also called PE cards or I/O cards.

● 測試頭中的電路,被用來提供輸入訊號到 DUT,並且接 客收從 DUT 輸出的訊號。也稱爲 PE 卡或 I/O 卡。

 

 

 

 

PMU

■ PMU

● The Precision Measurement Unit also called the Parametric Measurement Unit is used to make accurate DC measurements. The PMU is capable of forcing voltage and measuring current or forcing current and measuring voltage.

● 精密量測單元也稱作參數量測單元是用在精密的 DC 量測。PMU '能夠施加電壓量測電流或施加電流量測電壓。

 

 

Power Pin

■ Power Pin

● A device pin that is connected to a power supply or ground. VDD and VCC are typical examples of power pins. VSS and ground are also identified as power pins. Power pins have a structure that is different from signal pins.

● 要連接到電源供應器或接地端的元件接腳。Vdd 和 Vcc是典型的電源腳。Vss與接地也是電源腳。電源腳的結構與訊號腳是不同的。

 

 

 

Positive current

■ Positive current

● Current flowing from the test system into the device.

● 電流從測試系統流向 DUT 為正電流。

 

 

Preconditioning

■ Preconditioning

● Setting a device into the proper logic state so that a test may then be performed. A functional vector sequence is often required in order to prepare the DUT for a DC test.

● 設定元件到適當的邏輯狀態才能繼續進行測試。對於 DC 測試,通常需要功能的向量序列來將 DUT 準備在正確的狀態。

 

 

 

Pre/Post Burn-in

■ Pre/Post-Burn-in

● Pre/Post-Burn-In is testing devices before and after they are "burned in" to verify that the process did not cause certain parameters to drift. This process weeds out infant mortality devices.

● 在預燒程序之前與之後的元件測試，要驗證經過預燒之後不會造成某些參數漂移掉。此程序可淘汰掉早期死亡(infant mortality) 的不良品。

 

 

QA Test

■ QA Test

● Quality Assurance testing is performed on a sample basis to ensure that the package test was performed correctly.

● 品質保證測試是以抽樣檢查方式驗證封裝測試(package test)執行無誤。

 

 

 

RVS

■ RVS

● Reference Voltage Supplies are used to supply voltage references for logic 0 and logic 1 levels to the driver and comparator circuitry located on the pin electronic cards. These voltages are used to establish VIL, VIH, VOL, and VOH.

● 參考電壓供應器是用來提供驅動器邏輯0 或邏輯 1 的位準，還有 PE 卡上比較器電路的的 Vih、Vil 、Vu、Voh與 Vol位準。

 

 

Sense Line

■ Sense Line

● The Sense line is the non-current carrying line of a four-wire system such as a power supply. The sense line senses the voltage at the point where it is connected to the force line. The four wires of a four-wire system are the High Force, High Sense, Low Force, and Low Sense. In test systems, the Device Power Supply and the Precision Measurement Unit are four-wire systems.

● 爲如電壓供應器的四線系統的非電流運送線。感測線(sense line)感測連接到 force line 的端點電壓。在測試系統中，元件電源供應器 (Device Power Supply)與精密量單元(Precision Measurement Unit)為四線系統，四線系統的四線是 High Force、High Sense、Low Force與Low Sense。
 

 

 

Shared Resource

■ Shared Resource

● A test system resource that is limited in number and must be shared over multiple tester channels such as timing generators or a single PMU.

● 測試系統的資源有限必須讓多個測試通道共用資源如一個 PMU或時序產生器。

 

 

Signal Format

■ Signal Format

● The wave shape of an input signal supplied by the pin electronics driver circuitry.

● 由腳位電子卡的驅動電路所提供的輸入訊號波形。

 

 

 

Signal Pins

■ Signal Pins

● Input, output, Tri-State®, and bi-directional pins, not power or ground pins. Signal pins have a structure that is different from power pins.

● 訊號腳為輸入腳、輸出腳、三態與雙向腳，非電源腳或接地 腳。訊號腳的結構與電源腳是不同的。

 

 

 

Sink

■ Sink

● A term used to describe current flow from the test system into a device output pin (positive current). When an output is in the logic 0 states it can accept current from the test system which will flow through the device to the ground.

● 用來描述電流從測試系統流入元件輸出腳(正電流)的術語。當輸出 是在邏輯 0 的狀態,就可以接受從測試機來的電流並通過元件流到接地端。

 

 

 

Source

■ Source

● A term used to describe current flow from a device output pin into the test system (negative current). When an output is in the logic 1 state it can supply current which will flow from the DUT into the test system.

● 用來描述電流從元件流向測試系統輸出腳(負電流)的術語。當輸 出是在邏輯1的狀態,就可以提供從元件流向測試機的電流。

 

 

Static

■ Static

● This term indicates that the DUT is in a non-active condition, no input or output signals are changing.

● 用來指 DUT 是在非活動的情況的術語，沒有輸入或輸出訊號改變。

 

 

 

Test Cycle

■ Test Cycle

● The time duration of one test vector execution. The test cycle is based on the operating frequency of the DUT. The test cycle time can be determined by the formula: Cycle = 1/frequency. The test cycle is also known as the period.

● 一個測試向量執行的時間。也稱爲週期(period)。測試週期(testcycle)與 DUT的操作頻率有關。

 

 

Test Patterns

■ Test Patterns

● A representation of the states of inputs and outputs for the various logical functions that the device is designed to perform. Input data is supplied to the DUT by the test system. Output pattern data is compared against the response from the output pins of the DUT. During a functional test the test patterns are executed or applied to the DUT. In the event that the expected output data does not match the output data from the DUT a functional failure occurs. Test patterns are also called test vectors or truth tables. Test vectors are often represented as a sequence of ones and zeros or other characters which represent logical levels.

● 元件被設計所要表現的邏輯功能的輸入與輸出狀態的表 D示。輸入資料由測試系統提供給 DUT。輸出圖樣資料要與從 DUT 輸出腳 響應的結果作比較。在執行功能測試時,會執行測試圖樣(test pattern)並 且施加測試圖樣在 DUT 上。當所期望的輸出資料與從 DUT 輸出的資料 不一致時,功能測試失敗。測試圖樣(test pattern)也稱爲測試向量(test vector)或真值表(true table)。測試向量通常的表式法爲代表邏輯位準的 0 和1或其他字母的序列。
 

 

 

Test Philosophy

■ Test Philosophy

● A consensus of opinion of what is the best method of testing within a given company. It is based on their particular requirements, the selling price of their devices and often it is influenced by past experiences.

● 公司中認爲測試的最佳方法的一致信念。考量來自於公司的特別需求與元件的售價。常會被過去經驗所影響。

 

 

Test Program

■ Test Program

● The test program is what controls the test hardware in a manner that will guarantee that the DUT meets or exceeds all of its design parameters.

● 測試程式是控制測試硬體的方式，用以確定 DUT 符合或超 過設計參數。

 

 

 

Test System

■ Test System

● The test system is electronic and mechanical hardware used to simulate the operating conditions that the DUT will experience as it is used in the intended application, and separate good devices from defective ones. The test system is often referred to as ATE or Automated Test Equipment.

● 測試系統(test system)爲電子與機械硬體用來模擬 DUT 在未 來應用時的操作條件，並且將好的元件與有缺陷的元件分開。測試系統經常被稱 ATE 或自動測試設備(Automated Test Equipment)。

 

 

Test Vectors

■ Test Vectors

● See Test Patterns. Test vectors are also called test patterns or truth tables.

● 元件被設計所要表現的邏輯功能的輸入與輸出狀態的表 示。輸入資料由測試系統提供給 DUT。輸出圖樣資料要與從 DUT 輸出腳 響應的結果作比較。在執行功能測試時，會執行測試向量(test vector)並且 施加測試向量在 DUT 上。當所期望的輸出資料與從 DUT 輸出的資料不 一致時，功能測試失敗。測試向量(test vector) 也稱為測試圖樣(test pattern) 或真值表(true table)。測試向量(test vector)通常的表式法爲代表邏輯位準 的0和1或其他字母的序列。
 

 

 

Tester Channel

■ Tester Channel

● Circuitry on the pin electronics card which applies and/or processes voltage, current and timing for one DUT pin. Also called a tester pin.

● 測試通道(test channel)也稱作測試腳(test pin)。位於 PE 卡上的電路,對於一個 DUT 腳作施加或處理電壓、電流與時序。

 

 

Tester Per Pin

■ Tester Per Pin

● Each tester channel has its own resources, such as independent levels, timings, and PMU for each tester pin.

● 每一個測試通道有他自己的資源，如每個測試腳都有個別 的位準,時序與 PMU。

 

 

 

Three-State Output

■ Three-State Output

● A device pin that functions as an output pin but has the added capability of turning off (going to a high impedance state) Also called Tri-State® output.

● 元件腳的功能如同一個輸出腳，但是還有關閉的能力(高阻抗狀態)。

 

 

Truth Tables

■ Truth Tables

● See Test Vectors. Truth Tables are also called test patterns or test vectors.

● 元件被設計所要表現的邏輯功能的輸入與輸出狀態的表示。也稱爲測試向量(test vector)或測試圖樣(test pattern)。

 

 

 

UUT

■ UUT

● The semiconductor device being tested is often referred to as the DUT (Device Under Test). It is also sometimes referred to as a UUT (Unit Under Test).

● 在測試的半導體元件通常稱爲 DUT，有時也稱作 UUT(Unit Under Test)。

 

 

VCC

■ VCC

● The supply voltage for a TTL device.

● TTL 元件的供應電壓。

 

 

 

VDD

■ VDD

● The supply voltage for a MOS device.

● CMOS 元件的供應電壓。

 

 

VDDmax

■ VDDmax

● The lowest supply voltage at which a device is guaranteed to still operate correctly.

● 元件依然能保證正確的最大供應電壓。

 

 

 

VDDmin

■ VDDmin

● The highest supply voltage at which a device is guaranteed to still operate correctly.

● 元件依然能保證正確的最小供應電壓。

 

 

Vector Memory

■ Vector Memory

● A high speed memory which stores test vector information. Vector memory may also be called pattern memory.

● 用來儲存測試向量資訊的高速記憶體。也稱作圖樣記憶 體(pattern memory)。
 

 

 

VIH

■ VIH

● Voltage In High is the voltage value applied to input when applying logic 1. The VIH value represents the minimum guaranteed voltage value that can be applied to an input and still be recognized as logic 1 by the DUT circuitry.

● 施加邏輯1於輸入端的電壓值。 值代表可以被認爲是邏輯1的最小輸入電壓。

 

 

VIL

■ VIL

● Voltage In Low is the voltage value applied to input when applying a logic 0. The VIL value represents the maximum guaranteed voltage value that can be applied to an input and still be recognized as a logic 0 by the DUT circuitry.

● 施加邏輯0於輸入端的電壓值。值代表可以被認爲是邏輯0的最大輸入電壓。

 

 

 

VOH

■ VOH

● Voltage Out High is the voltage value produced by an output when driving a logic 1. The VOH value represents the minimum guaranteed voltage value that will be produced by the output when driving out a logic 1. 

● 將輸出驅動成邏輯1的輸出電壓值。Voh 值代表被認爲是邏輯1的最小的輸出電壓。

 

 

VOL

■ VOL

● Voltage Out Low is the voltage value produced by an output when driving a logic 0. The VOL value represents the maximum guaranteed voltage value that will be produced by the output when driving out a logic 0.

● 將輸出驅動成邏輯0的輸出電壓值。Vol 值代表被認爲是邏輯0的最大的輸出電壓。

 

 

 

VREF

■ VREF

● The reference voltage is associated with the dynamic loads. VREF controls the switching point of IOL and IOH currents.

● 與動態負載相關的參考電壓。Vref控制 Iol 與 Ioh的切換點。

 

 

VSS

■ VSS

● The power pin provides a return path for the power supplied to the VDD or VCC pin.

● 爲元件電源腳。

 

 

 

Wafer Test

■ Wafer Test

● Testing of individual devices when they are still in wafer form. This is the first attempt at separating the good die from the bad. This activity is also referred to as wafer sort.

● 測試在晶圓上的元件, 區分出好的晶粒與壞的晶粒。也稱作 Wafer sort。