隨手記錄

The IO board receives the reference oscillator signal from the clock board and creates four-vector periods selectable on-the-fly through sequencer commands or by assignment to time sets. The vector period is an integer multiple of the reference oscillator (ROSC).

IO從CLK接收ROSC信號，並經由SEQ產生四個可即時選擇的Vector週期或指派到time sets. Vector的週期是ROSC的整數倍。

Allows the programmer to run selected pins under different data rates. Multi-clock cycles can be defined for each of the four periods and the periods are then assigned to a time set or selected using a sequencer command.

程式撰寫者(工程師)可以執行不同的資料速度(Data Rate)在選定的Pins上。多重的CLK cycle可定義到四個週期。而這個Period則會被指派到time set 或被SEQ的指令所選擇。

The SC series is a per-pin system that provides six timing edge generators for each channel. Each timing edge generator can have four timing values selectable on-the-fly and is implemented as part of the V-Chip.

SC系列是一個per-pin的系統，對每根Pin都可以提供6個 timing edge. 每個timing edge可具有4個可即時選擇的timing values.

The six timing generators are dedicated to controlling the following:

• Two control the drive data that is driven to the DUT.
• Two control the driver to be in an active or tri-state mode.
• Two control the error logic circuit to strobes.

Strobes are generated by the two-timing edges dedicated to this purpose. Strobing may be performed in either edge or window mode.

• Window Mode
  • Two timing edges comprise the start (rise) and stop (fall) of the strobe window. Only DUT outputs occurring inside the window are evaluated in the error detection circuit. This is also the mode used to detect DUT glitches. The minimum strobe is 5 ns.

• Edge mode
  • Two timing edges are used for separate strobing of a high and low comparator; the rising edge of the strobe is used to clock the status of the high comparator, and the falling edge of the strobe is used to clock the status of the low comparator. the DUT state is then compared with the expected data which results in a pass or fail condition.

When the driver is enabled, the drive levels (0 and 1) are controlled by the two timing edges dedicated to the purpose of providing specific formatting characteristics that implement all classical ATE formats.

The integrated pin electronics has full per pin programmability of all analog levels. the pin electronics is implemented with a custom analog hybrid, which is located close to the DUT to ensure the best signal integrity.

The per pin programmability of the seven analog reference levels (VIH, VIL, VOH, VOL, IOH, IOL, VCM) are produced by a single voltage reference generator scanned to sample and hold circuits.

A reference memory table stores this information for each analog reference set. This allows for quick changing from one table or set of input conditions to another. This is an important feature in high volume production testing.

IO Control：During the time the driver is active or enabled, the input circuitry to the active loads is in tri-state or off condition. This prevents the loads from interfering with the drive output signal.

During the time the drive is tri-stated or disabled., the input circuitry to the active load levels are enabled, this type if switching between the two enables the test engineer to drive and compare n the same cycle.

The logical conditions that are sent to the device under test are contained in the pattern vector memory of the I/O board. Each DUT pin channel has up to 4 Mb of vector memory and each I/O board contains all the vector memory for 16 DUT pins.

On the SC series, pattern generation can include but is not limited to fill multi-state vector notation(1 ,0, L, H, X, Z), and user-defined character sets. The characters defined to control how and when each pin drives, tri-states, or compares.

在SC系列機台囙，Pattern產生的各種狀態是以填入以下符號 (1 ,0, L, H, X, Z)，包含但並不局限。使用者也可以自行定義符號。這些符號定義著這些Pin如何動作，如drive, tri-state 或 compare.