隨手記錄

SC312 Tester - Sequencer Board Functional Description(SEQ板子 功能描述)

The sequencer is a shared resource (not per pin) which provides a hi-speed control function for I/O boards. The sequencer functions as a very high-speed state machine where each new state or cycle provides DUT data and or pattern control data for the next cycle. Like all system modules, the overall control of the sequencer comes to form the CPU subsystem and its stored program. 

During the Tester Mode, the Sequencer is the Master whereases as I/O Boards are the Slaves. Thus the Sequencer provides all necessary control signals to the I/O boards. These signals are : RUM, P1, P0, and IFAIL(used by  V-chip) and VLD, VLE, and VCE (used by Memory).

Before the Tester Mode begins, all appropriate bits of the registers must be programmed including V-Chip Register, I/O Board  Registers, and All Memory (VM, TM and CM).

The sequencer controls the following major areas：

• Bus interface and control：
  • The Sequencer interfaces to the CPU via the HVS data bus which supports 32 bits of data and up to 30 bits of the address.

• Load Board control：
  • The sequencer interfaces to the DUT Load via pogo pins. There are eight each, address, and data line signals, that can control external circuitry on the load board. Sixteen relay drive signal and a sequencer command sync pulse, pin 31,  are also provided.

• I/O control
  • The sequencer provides all high speed and test pattern control signals to the I/P boards. All input control signals are recaptured by ROSC on entry to the receiving I/P board before being passed on the V-Chip or address.

• Local memory operation
  • The local memory operation is a complex function that is broken down into sub-block.

• Period generation
  • A Cycle is generated using ROSC. Ram memory stores up to 12 sets of period values and the time set memory allows the progrm=ammer to select form any value on a cycle-to-cycle basis. The user has access to four of period values, the other eight are for time insertions required for a non-sequential vector (jump or loop and same cycle matching.

• Pattern control, opcode decoding
  • Dedicated fields in local memory provide for all dynamic pattern control functions. These fields are decoded for every cycle and the appropriate action is taken.

• Pattern starting and stopping
  • A functional pattern can be started or stopped on any line in local memory, The pattern is started by placing a "jump to strat address " in the last location of vector memory.

• Ignore fail
  • The vector pattern always stops on a fault unless the STPONFL(stop on fault) bit is inactive. Fail from the DUT can be ignored for all or part of the pattern, A fail can be ignored completely or until a predetermined condition is met. During this mode, the V-chip does not log or react to failures and sends a fil signal to the sequencer on each occurrence.

•  Non-sequential(branching) operation
  • This opcode causes the transfer to the specified address in local memory.

• Repeat counts
  • Any DUT pattern can be created from 2 to 65536 times before incrementing to the next location of memory.

• Continuous mode
  • When a continuous loop or repeat is entered, the loop or repeat is executed once before beginning continuous mode. At this time, the sequencer fives control of the tester bus (HVS data bus) back to the CPU a continuous to execute the loop indefinitely.  After an interrupted form the CPU or DUT is received, the loop executes until the loop count reached zero.

• Match Mode
  • Pattern flow can be DUT pass/fail dependent by entering the match mode of operation. In match mode, the IFAIL signal is sent to the I/O board so that the V-Chip does not log any functional failures; however, the V-Chip does send the pass/fail status back to the sequencer. at the end of each cycle, the sequencer evaluates the DUT response and establishes either a match or no match condition.
  • Match mode remains active until a match or an error condition occurs (e.g., one possible error condition is a time out condition before a match condition is achieved ).

• Loop Counts
  • Any DUT pattern can be repeated form 2 to 65536 times before incrementing to the next location of vector memory.